The present invention is generally directed to a process for the fabrication of thin film field effect structures useful in matrix addressed liquid crystal displays (LCSs). The present invention is also directed to structures produced in accordance with the process. More particularly, the present invention is directed to the utilization of dual dielectric materials for isolating gate metallization layer material from other conductive structures present in matrix addressed liquid crystal displays. Even more particularly, the present invention is directed to one solution for material process compatibility problems and to the problem of pixel element discharge during off cycles.
A liquid crystal display device comprises a pair of flat panels sealed at their outer edges and containing a quantity of liquid crystal material. These liquid crystal materials typically fall into two categories: dichroic dyes and a guest/host system or twisted nematic materials. The flat panels generally possess transparent electrode material disposed on their inner surfaces in predetermined patterns. One panel is often covered completely by a single transparent "ground plane" or "back plane" electrode. The opposite panel is configured with an array of transparent electrodes, referred to herein as "pixel" (picture element) electrodes. Thus, a typical cell in a liquid crystal display includes liquid crystal material disposed between a pixel electrode and a ground electrode forming, in effect, a capacitor-like structure disposed between adjacent front and back panels.
It is noted that transparency is generally required for only one of the two panels and the electrodes disposed thereon.
In operation, the orientation of liquid crystal material is affected by voltages applied across electrodes disposed on opposite sides of the liquid crystal material. Typically, voltages applied to the pixel electrode effect a change in the optical properties of the liquid crystal material. This optical change causes the display of information on the liquid crystal display screen. In conventional digital watch displays and in some LCD screens used in miniature television receivers, the visual effect is typically produced by variations in reflected light. However, the utilization of transparent front and back panels and transparent electrodes also permits visual effects to be produced by transmissive effects. These transmissive effects may be facilitated by separately powered light sources for the display, including fluorescent light type devices. LCD display screens may also be employed to produce color images through the incorporation of color filter mosaics in registration with the pixel electrode array. Some displays may also employ polarizing filters to either enhance or provide the desired visual effect.
Various electrical mechanisms are employed to sequentially turn on and off individual pixel elements on an LCD screen. For example, metal oxide varistor devices have been employed for this purpose. However, the utilization of thin film semiconductor switch elements is most relevant herein. In particular, the switch element of the present invention comprises a thin film field effect transistor (FET) employing a layer of amorphous silicon. These devices are preferred in LCD devices because of their potentially small size, low power consumption, switching speeds, ease of fabrication and compatibility with conventional LCD structures. However, fabrication processes for certain desired semiconductor switch element structures have been found to be incompatible with the employment of certain materials used in the transparent LCD electrodes. It is seen that while certain physical FET structures or LCD devices are desirable, it is often extremely difficult to devise processes that satisfactorily produce the desired structure. Moreover, in any process of the kind contemplated herein, the number of masking steps is desired to be low since, in general, the greater the process complexity, the lower is the reliability of the resulting device and the process yield. One of the material problems that can arise in the fabrication of thin film FETs for LCD screens is the problem of providing good electrical contact between source and drain line metal and the amorphous silicon layer of the FET. In general, molybdenum is a desired metal to employ for source and drain electrode pads, but molybdenum may not exhibit good electrical contact with intrinsic amorphous silicon. A thin layer of aluminum disposed between the molybdenum and the amorphous silicon may be provided as discussed in previously filed application Ser. No. 761,939, filed Aug. 2, 1985, which is assigned to the same assignee as the present invention. However, care must be taken to avoid etchant compatibility problems with indium tin oxide which is preferably employed for the pixel electrodes. Moreover, aluminum has a tendency to diffuse into silicon material, thus potentially degrading device performance particularly if high temperatures are employed in subsequent process steps. Another problem encountered in LCD devices is the tendency for capacitive discharge to occur during off cycles. In this situation, the capacitor formed by the pixel electrode, the ground plane electrode and the liquid crystal material as a dielectric, tends to discharge through the FET if the FET device characteristics are inappropriate. In particular, it is desirable to limit FET current under conditions of reverse gate voltage. If the source-drain current is high under these conditions, capacitive leakage tends to occur and this can affect display quality. It is also desirable that the current-voltage characteristics do not exhibit large hysteresis loops since this can result in voltage uncertainty on the pixel electrode.
Attention is now specifically directed to particular problems of FET and LCD fabrication. In other processes for the manufacture of thin film FET devices on substrates for use in LCD displays, the gate and drain electrodes are formed on substantially the same plane. This arrangement has three undesirable effects. First, such arrangements permit gate metal to be exposed during later stages of processing. Since the gate metal may be attacked by subsequent process chemicals, this limits the choice of gate and also of source and drain materials as well as the choice of useful process procedures. One solution to this problem is the utilization of titanium as a gate metal and molybdenum as a source and/or drain metal. However, aluminum is a more desirable choice for the gate metal in that it exhibits a higher electrical conductivity and is more optically opaque than titanium. Optical opacity for gate material is desired to reduce light induced charge leakage through the FET. However, aluminum is attacked by most wet etchants which also etch molybdenum and can also react with indium tin oxide in the transparent pixel electrode material to produce a so-called "Swiss cheese effect" on the pixel elements.
Secondly, there is a significant possibility of short formation between the gate and source-drain and gate and pixel electrodes when these metal patterns occur on the same level of the substrate. These shorts often occur because of excess metal being left after photolithography and etching. It has been observed by the present inventors that occurrences of these excess metal defects result in significant yield limitation.
Thirdly, there is a possibility of leakage paths forming between the source and drain electrodes and the gate electrode along the edge of silicon/silicon nitride island structures which provide the foundation for thin film field effect transistors. Leakage paths also can form along the sidewalls of these islands. This problem can be increased by residues which are left after plasma and metal etching. This can cause leakage between the data line and the gate line and between the pixel electrode and the gate line, and in some cases, between the source (pixel electrode) and drain electrode. Data-line-to-gate-line leakage is undesirable because it causes an unnecessary load on the gate line drivers, and more importantly, it makes identification of other more significant leakage paths within the array more difficult. This can be a problem in testing and repair of the arrays. Other problems of leakage between the source and drain electrodes or between pixel and gate electrodes can also be very serious since such leakage increases the off current of the device and therefore, the decay rate of the charge stored on the pixel electrode. These leakage paths can be due to residues along the edges of the silicon islands. Scanning electron microscopic (SEM) examination indicates that residues can occur along this edge and devices with these residues often have increased off current levels.